Western Digital Corporation
Domain of Research: ,
I am a Principal R&D Engineer at Western Digital Corporation Research. I earned PhD degree in Computer Engineering from Chalmers University of Technology, Sweden in 2013. My current works include develop advanced memory controllers (e.g. NVDIMM-P) for Storage Class Memory (SCM) system and hierachical dynamic wear-leveling techniques to improve both lifetime and security of NVM-base systems. Previous works include a) design and integrate Network-on-Chip (NoC) IPs and multi DSP cores systems for space industry b) accelerator-based highly programmable and energy efficient heterogeneous systems c) low power circuit design and methodology (arithmetic, VLSI for digital signal processing etc.). I have been as senior hardware design engineer at Recore Systems BV, post-doctoral at University of Chicago, and visiting researcher at Interuniversity Microelectronics Centre (IMEC).